![]() ![]() Std::thread t(do_work,16) // 16 ints = 64 bytes, one cache line away Trivial approximation of useful work done by a thread Volatile int arr // place in memory threads do their work So even though this program was very fast (5.2ns/call): enum // a large number, to outweigh thread creation overhead This means address 0x0ABCD and address 0x1ABCD (which are 64KB apart) both get mapped to the same place in the cache. ![]() Direct mapping means elements 1 and 2 will go into different adjacent slots, but you can support many elements.įor example, the Pentium 4's L1 cache was 64KB in size and direct-mapped. ![]() The simplest approach is a " direct mapped cache ", where element X goes into cache slot X%N (where N is the size of the cache). Generally, you face this problem when you've got a new element X to load into the cache-which cache slot do you place X into? Set-associative Cache MappingĪnytime you have a cache, of any kind, you need to figure out what to do when the cache gets full. Because a fully associative comparator like above would get very expensive for thousands of lines, a real cache is "set associative", allowing a given address to live in only one of a few possible cache lines, such as a 4-way associative cache using the comparator circuit above. In a real CPU, cache uses 32 byte or 64 byte cache lines (this saves tag bits), and stores thousands of lines. In a real CPU, the cache hit line is used to stall the pipeline if the data being read is not in the cache, and activate a fetch out to RAM. This is a 4-line single-byte cache, and I've omitted the process by which cache lines are allocated, and data is written into the cache. The gate design of a cache is surprisingly subtle. RAM is much bigger, 2GB, but only 3GB/sec. L2 cache is larger, 4MB, but can be read at 13GB/sec. L1 cache is only 32KB, but can be read at 28GB/sec. Here's a screenshot from Memtester on a 2GHz Core 2 laptop. Multicore Cache Coherence Protocols Cache Design, and Multicore Cache Coherence ![]()
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